A tri-level current-steering DAC design with improved output-impedance related dynamic performance
conference contribution
posted on 2020-01-30, 09:51 authored by Shantanu Mehta, Anthony G. Scanlan, BRENDAN MULLANEBRENDAN MULLANE, Daniel O'HareThis paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-to-analogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces output-impedance related distortion. The technique demonstrates ~10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.
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2019 17th IEEE International New Circuits and Systems Conference (NEWCAS);Publisher
IEEE Computer SocietyNote
peer-reviewedOther Funding information
SFI, EIRights
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