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A tri-level current-steering DAC design with improved output-impedance related dynamic performance

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conference contribution
posted on 2020-01-30, 09:51 authored by Shantanu Mehta, Anthony G. Scanlan, BRENDAN MULLANEBRENDAN MULLANE, Daniel O'Hare
This paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-to-analogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces output-impedance related distortion. The technique demonstrates ~10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.

History

Publication

2019 17th IEEE International New Circuits and Systems Conference (NEWCAS);

Publisher

IEEE Computer Society

Note

peer-reviewed

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SFI, EI

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© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Language

English

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