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An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test

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conference contribution
posted on 2020-01-29, 16:35 authored by BRENDAN MULLANEBRENDAN MULLANE, Vincent O'Brien
This paper presents a processor architecture for Fast Fourier Transform computation of real-valued signals for on-chip analog to digital converter test and evaluation. The design performs a radix-2 technique optimized for low area overhead and easy integration into system on chips. The hardware logic supports variable transform lengths and accurate parameter extraction. The processor has been validated on 0.18um CMOS silicon and applied to a data converter test application for extraction of dynamic parameters that are SINAD, SFDR and THD. The architecture is suitable for safety-critical applications where spectral integrity of the converter signal path can be run at start-up or during interval down times

History

Publication

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS); pp. 591-594

Publisher

IEEE Computer Society

Note

peer-reviewed

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© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Language

English

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