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Arshak Improving the performance.pdf (6.04 MB)

Improving the performance of an FPGA based model design for sensor monitoring using PlanAhead tool

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conference contribution
posted on 2011-07-21, 09:28 authored by Khalil Arshak, Essa Jafer, Christian Serge Ibala
The study in this paper is focused on the improvement of a Field Programmable Gate Arrays (FPGA) based design using a hierarchical analysis tool offered by XILINX PlanAhead'TM. During this work, PlanAhead software is used to address any problems on the physical side of our FPGA design flow in order to add more visibility and control. The target system is reading analog information recorded by a biomedical sensor in a transmitting unit attached to the patient. The recorded data is converted digitally using analog to digital converter (ADC) and sent to FSK transmitter through FPGA. Verilog HDL has been used to develop and implement the required functions of the FPGA, such as bus interfacing, data buffering, compression and framing. The system performance has been optimized using a recent comprehensive tool in order to reach and maintain the goals of the design.

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Electronics Technology;

Publisher

IEEE Computer Society

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peer-reviewed

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©2006 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.

Language

English

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