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Power testing of an FPGA based system using modelism code coverage capability

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conference contribution
posted on 2011-07-01, 16:02 authored by Khalil Arshak, Essa Jafer, Christian Serge Ibala
Field programmable gate arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip designs. Nevertheless, FPGA vendors can not accurately specify the energy consumption information of their products on the device data sheets because the energy consumption of FPGAs is strongly dependent on target circuit including resource utilization, logic partitioning, mapping, placement and route. While major CAD tools have started to report average power consumption under given transition activities, energy optimal FPGA design demands more detailed energy estimation. The target design is telemetry system used for health monitoring applications. The FPGA is acting as the controller unit of both transmitter and receiver. Transmitter side is reading data from interfaced sensors. Verilog-HDL has been used to implement the required functions of the FPGA. In this paper, the power performance of the FPGA based design will be investigated using XILINX Xpower tool. Modelsim Code coverage feature has been incorporated to make sure that the test-bench cover all the nets branch statement of the design and create the most accurate Value Change Dump (VCD) file for the power consumption estimation.

History

Publication

DDECS '07. Design and Diagnostics of Electronic Circuits and Systems, 2007.

Publisher

IEEE Computer Society

Note

peer-reviewed

Rights

©2007 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.

Language

English

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