posted on 2012-04-25, 15:55authored byEamonn Linehan, Siobhán Clarke
The cost of correcting errors in the design of an embedded system's hardware components can be higher than for its software components, making it important to test as early as possible. Testing hardware components before they are implemented involves verifying the design through either formal or more commonly, simulation-based functional verification. Performing functional verification of a
hardware design requires software-based simulators and veriification testbenches.
However, the increasing complexity of embedded systems is contributing to test-benches that are progressively more difficult to understand, maintain, extend and reuse across projects. This paper presents an aspect-oriented domain-
specific modelling language for the e hardware verification language that can be used as part of a model-based software engineering process. The modelling language is designed to produce well modularised models from which e code can be generated, thereby improving engineers ability to develop testbenches
that can be more easily maintained, adapted and reused. We demonstrate the suitability of the modelling language through its application to a representative testbench from the automotive semiconductor industry.
History
Publication
Journal of Systems Architecture;2011
Publisher
Elsevier
Note
peer-reviewed
Other Funding information
SFI
Rights
Open Access
this is the author’s version of a work that was accepted for publication in Journal of Systems Architecture. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Journal of Systems Architecture. doi10.1016/j.sysarc.2011.02.001