posted on 2017-10-18, 11:17authored byJames Mooney, Mark HaltonMark Halton, Abdulhussain E. Mahdi
This paper describes a Digital Signal Processor (DSP) whose
architecture has been purposely developed for executing power converter control
algorithms. It is intended for use in the control of multi-phase or multi-rail
switching power converters. The DSP's novel dual multiplier-accumulator
datapath allows multiple operations to be executed in a single clock cycle,
thus shortening required execution times of power control algorithms compared
with standard low-end DSPs. The processor has been designed using the Verilog
Hardware Description Language (HDL), implemented on an FPGA development board
and tested in a closed-loop system controlling three independent 500 kHz
synchronous buck converters.
History
Publication
Applied Power Electronics Conference and Exposition (APEC);pp. 2207-2211