Design of high order mismatch and ISI shaping dynamic element matching decoders for delta sigma data converters

This thesis presents the analysis and design of dynamic element matching (DEM) decoders targeted at both discrete and continuous time oversampling delta sigma data converters. Discrete time delta sigma data converters require a linear DAC in the signal path. Mismatch present on the DAC elements leads to non-linearities in the DAC transfer function, degrading the signal to noise ratio of the converter. In this work, a DEM scheme designed to operate at low oversampling rates is developed. The proposed design employs a 4th order filter optimized to provide shaping of the mismatch error over a wider signal bandwidth. The design achieves greater suppression of mismatch error at low to medium oversampling rates compared to conventional high order DEM decoders. In continuous time delta sigma data converters, the finite matching of circuit elements leads to an additional source of error when the elements turn on and off, this intersymbol interference (ISI) error is not shaped using conventional DEM approaches. To mitigate the ISI error, a design whereby the DEM decoder deterministically controls the element transitions is proposed. The decoder selects the on and off transitions so that they form two independent signals allowing the ISI error to be removed from the signal band. The decoder design provides significantly more ISI error suppression than previously published techniques. In addition to improving the performance of the DEM algorithms, techniques are developed to split the DEM decoders into multiple sub DEM blocks, these techniques allow for a reduction in the logic required by the decoders, making the designs more amenable to integration.