Sources of iteration and a risk mitigation methodology in semiconductor new product development projects

Iteration is the major source of risk in semiconductor New Product Development (NPD) projects, occurring in approximately 90% of projects and causing on average approximately 30% schedule slippage. As such, iteration risk in semiconductor NPD projects is a very important issue that needs to be addressed. NPD projects bring specific challenges for a company due to the innate uncertainty involved in producing a new product. One major consequence of the inherent uncertainty involved in NPD projects is the resultant uncertainty and risk of iteration in project schedules. A challenge when trying to generate a product development schedule is to accurately account for the uncertainty caused by iteration and potential schedule slippage. The occurrence of iteration in NPD projects can directly lead to budget over-runs, schedule delays and missed product release. With time to market often being an important determinant of NPD success any factor that can potentially cause project delay must be fully understood. This research aims to further examine iteration risk in a semiconductor NPD project context, and explore how a more accurate iteration risk mitigation methodology can be established. Providing management within a firm with a process specific risk analysis regarding iteration can enable a proactive approach to NPD scheduling and contingency planning. The goal of the research is to provide an iteration risk analysis methodology where the risks of delay due to iteration in NPD projects can be identified, quantified and subsequently mitigated. A semiconductor case study company is used for the development of the risk analysis framework that aims to provide a new approach for analysing iteration risk in NPD projects. Iteration was found to be a dominant source of risk in this semiconductor NPD project environment. Investigation into the company’s NPD process, and the specific problem of iteration, identified a number of sources that contribute to iteration risk in their projects. Through the analysis of iteration in NPD in the case study firm, five general areas were identified as being contributory factors to the occurrence of iteration in semiconductor NPD projects: [1] simulation coverage, [2] requirements definition, [3] new process/technology risk, [4] human resources and [5] project planning. Follow up interviews and analysis of the five general areas resulted in the identification of 49 specific project characteristics that are used to fully define the initial conditions of an NPD project in the firm. The developed risk mitigation methodology uses the inputs for these characteristics in conjunction with historical project performance data to produce a schedule risk analysis for a current NPD project. The methodology employed uses a novel approach to defining iteration risk that uses the root causes in a process to analyse the potential schedule risk of an NPD project. To gain a deeper understanding of the methodology, data was collected for the characteristics for a sample of 30 past NPD projects. This data was used to further investigate the risk due to iteration and subsequent schedule slippage in these projects. This investigation demonstrates how the developed methodology can be deployed in a practical setting to enable the company to proactively minimise iteration risk in their NPD projects. Using the developed methodology provides a company with a sustainable approach for analysing iteration risk and facilitates ongoing organisational learning in relation to the management of product development schedules. The methodology provides a structured approach for better understanding and mitigation of iteration risk in semiconductor NPD projects.