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Fault analysis in triple data encryption standard algorithm using modified decision tree algorihtm
Date
2026-09-01
Abstract
This work proposes a modified decision tree algorithm to investigate the attacks in the Triple Data Encryption Standard Algorithm. The modified Decision Tree algorithm includes the equality checker logic to validate the correctness of the values in the iterative rounds of the Triple DES algorithm. The successfully checked iteration values are identified for attacks using the modified decision tree algorithm. Among various cryptography algorithms, the Triple DES algorithm is highly secure due to its complexity in design; however, due to its design complexity, the possibility of meet-in-the-middle attacks is maximum. To optimize this trade-off, the Triple DES algorithm is selected and incorporated with an automatic fault indication algorithm. The proposed method investigates the possible fault occurrence in the Triple DES algorithm by inducing random attacks within the algorithm with the response time of 5.075 ms. The developed fault investigation algorithm is implemented in the Xilinx Artix 7 FPGA device to attain the low latency of 5.335 ns and throughput of 1.1996 Gbps. The System-On- Chip Layout for the proposed method is designed to analyze the VLSI parameters of speed, area, and power.
Supervisor
Description
Publisher
Elsevier
Citation
Franklin Open 16, 100672
Files
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Prathap_2026_Fault.pdf
Adobe PDF, 5.81 MB
ULRR Identifiers
Funding code
Funding Information
Sustainable Development Goals
External Link
License
Attribution-NonCommercial-ShareAlike 4.0 International