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A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a low voltage CMOS process
Date
2012
Abstract
Direct Digital Synthesis (DDS) systems generate fine frequency resolution signals over a broad spectrum that are used in a wide variety of applications such as multi-mode RF, communications, measurements and test. A high performance DDS band-pass Digital to Analog Converter (DAC) architecture and implementation is presented that delivers high spectral purity over a narrow-band response. The low power D/A Converter is portable to standard CMOS processes and designed to achieve over 100dB narrow-band SFDR performance using Sigma-Delta (ΣΔ) modulation and multi-bit current steering techniques. A 3rd order digital ΣΔ modulator is combined with a 4th order digital Dynamic Element Matching (DEM) block to shape the noise while calibrating for process mismatch variations. A low silicon area output stage is used to deliver a high performance specification.
Supervisor
Description
peer-reviewed
Publisher
Springer
Citation
VLSI-SoC: Advanced Research for Systems on Chip. Salvador Mir, Chi-Ying Tsui, Ricardo Reis, Oliver C. S. Choy (eds);pp. 144-157
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Files
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Mullane_2012_100dB.pdf
Adobe PDF, 1.86 MB
ULRR Identifiers
Funding code
Funding Information
Enterprise Ireland (EI), Industrial Development Agency (IDA)