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Publication

A reduced hardware ISI and mismatch shaping DEM decoder

Date
2017
Abstract
This paper presents a dynamic element matching (DEM) decoder incorporating both intersymbol interference (ISI) and mismatch error shaping. From the analysis of ISI error in multi-bit DACs, an algorithm is developed that deterministically controls the element transitions, such that on each conversion cycle the instantaneous number of on transitions is set to a constant value, while the instantaneous number of off transitions varies with the decoder input signal. The technique achieves greater ISI error mitigation than previous approaches using less hardware. To further reduce the logic area, a hierarchical DEM structure, whereby the DEM decoder is split into multiple sub-DEM decoders, is presented.
Supervisor
Description
peer-reviewed
Publisher
Springer
Citation
Circuits Systems and Signal Processing; 37 (6), pp. 2299-2317
Collections
Electronic & Computer Engineering
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CSSP_rev3.pdf
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Keywords
Delta sigma Digital-to-analog converter (DAC), Dynamic element matching (DEM), Element selection logic (ESL)
ULRR Identifiers
https://researchrepository.ul.ie/handle/10344/6210
 https://doi.org/10.34961/3998
Funding code
Funding Information
Enterprise Ireland (EI), European Research Council (ERC)
Sustainable Development Goals
External Link
Type
Article
Rights
https://creativecommons.org/licenses/by-nc-sa/1.0/
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