Loading...
An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test
Date
2018
Abstract
This paper presents a processor architecture for Fast Fourier Transform computation of real-valued signals for on-chip analog to digital converter test and evaluation. The design performs a radix-2 technique optimized for low area overhead and easy integration into system on chips. The hardware logic supports variable transform lengths and accurate parameter extraction. The processor has been validated on 0.18um CMOS silicon and applied to a data converter test application for extraction of dynamic parameters that are SINAD, SFDR and THD. The architecture is suitable for safety-critical applications where spectral integrity of the converter signal path can be run at start-up or during interval down times
Supervisor
Description
peer-reviewed
Publisher
IEEE Computer Society
Citation
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS); pp. 591-594
Collections
Files
Loading...
MWSCAS_conf_paper.pdf
Adobe PDF, 1011.87 KB
Funding code
Funding Information
Sustainable Development Goals
External Link
Type
Meetings and Proceedings
Rights
https://creativecommons.org/licenses/by-nc-sa/1.0/