Managing hardware verification complexity with aspect-oriented model-driven engineering

Recent advances in both the capabilities and accessibility of embedded systems have resulted in the potential to build increasingly complex systems that consequently are difficult to develop, test and deploy. Model-driven approaches raise the level of abstraction at which developers work, promising improved quality (reliability, safety, real-time properties) and increased productivity through automation. However, despite the increasing application of model-driven technologies to the development of embedded systems, little attention has been paid to the corresponding increase in complexity of verification environments for embedded systems. As system complexity has increased in recent years so has the complexity of hardware verification testbenches resulting in them becoming difficult to understand, maintain, extend and reuse across projects. This paper presents a new UML profile for the e verification language that enables the use of an aspect-oriented, model-driven approach for the design of verification testbenches.