Analysis of feedback predictive encoder based ADCs

Purpose The purpose of this paper is to present analysis of the feedback predictive encoder based ADC (Analog-to-Digital Converter). Design/methodology/approach The use of feedback predictive encoder based ADCs presents an alternative to the traditional two stage pipeline ADC by replacing the input estimate producing first stage of the pipeline, with a predictive loop that also produces an estimate of the input signal. Findings The overload condition for feedback predictive encoder ADCs is dependent on input signal amplitude and frequency, system gain and filter order. The limitation on the practical useable filter order is set by limit cycle oscillation. A boundary condition is defined for determination of maximum useable filter order. In a practical implementation of the predictive encoder ADC, the time allocated to the key functions of the gain stage and loop quantizer leads to optimisation of the power consumption. Practical implications A practical switched capacitor implementation of the predictive encoder based ADC is proposed. The power consumption of key circuit blocks is investigated. Originality/value This paper presents a methodology to optimise the bandwidth of predictive encoder ADCs. The overload and stability conditions may be used to determine the maximum input signal bandwidth for a given loop quantizer. Optimisation of power consumption based on the allocation of time between the gain stage and the SAR ADC operation is investigated. The lower bound of power consumption for this architecture is estimated.