ctip_vlsi_ieee_v3_internal.pdf (958.17 kB)
Bandwidth enhancement to continuous-time input pipeline ADCs
journal contributionposted on 2023-03-03, 12:13 authored by Daniel O'Hare, Anthony G. Scanlan, Eric Thompson, BRENDAN MULLANEBRENDAN MULLANE
This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the medium resistive input benefit of CTIP ADCs. The resetting integrator allows the architecture to be implemented with a feedforward compensated op-amp using low-voltage CMOS processes. This paper has been verified by simulation results of a CTIP ADC with 1.2-V supply voltage designed in TSMC's 65-nm CMOS technology.
PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems;26 (2), pp. 404-415
PublisherIEEE Computer Society
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Department or School
- Electronic & Computer Engineering
- Computer Science & Information Systems