Traffic-aware adaptive polling mechanism for high performance packet processing

Traffic-Aware Adaptive Polling Mechanism for High Performance Packet Processing Hristo Trifonov The work described in thesis concerns the topical subject area of SDN (software defined networking), in particular the Data Plane architectures. High-speed network interfaces of 10 GB/s and more are widely used in today’s data centres. The increased performance of modern multi-core commodity servers allows for network packet processing functionalities to be implemented in Linux user space with the use of specialised software frameworks, which bypass the Linux kernel network stack and essentially obviates the need for dedicated network hardware components. A drawback for a number of such frameworks is related to the underlying architectural design where all network devices are accessed using polling mode instead of interrupt driven mode. This leads to high CPU core utilization and an increased power demand by the packet processing system, which results in inherent inefficiencies. A specific problem is explored where such inefficiencies are known to exist in the Data Plane Development Kit (DPDK), due to the high polling frequency of the DPDK’s packet sampling scheme. This thesis describes a novel approach to reduce such inefficiencies, where the design, implementation and evaluation of a new Adaptive Polling Mechanism (APM) is presented within the receiving loop of the DPDK’s packet processing framework. The APM implementation focuses on reducing the polling frequency of the dedicated relevant CPU core(s). To evaluate the new proposed approach a full experimental laboratory setup, that includes the hardware equipment as well as the software configurations, is developed as a ‘test bench’ for the research. Two experimental case studies are developed to evaluate the effectiveness of the new approach. The related energy consumption by computing resources that are using the DPDK is experimentally measured and presented. The results of this research work show that the proposed adaptive polling mechanism reduces the polling frequency of the CPU core, and can lead to an increased application efficiency of up to 60%, according to the experimental results. Further it is seen that the proposed adaptive polling mechanism can reduce the energy consumption of the Data Plane’s forwarding core(s) per ‘processed Ethernet packet’, and reduces the overall instantaneous system power demand by up to some 6.5W at low line rates.