Indino_2017_open.pdf (1.89 MB)
An open source platform and EDA tool framework to enable scan test power analysis testing
thesisposted on 2022-09-02, 12:50 authored by Ivano Indino
Ivano Indino Scan testing has been the preferred method used for testing large digital integrated circuits for many decades and many electronic design automation (EDA) tools vendors provide support for inserting scan test structures into a design as part of their tool chains. Although EDA tools have been available for many years, they are still hard to use, and setting up a design flow, which includes scan insertion is an especially difficult process. Increasingly high integration, smaller device geometries, along with the requirement for low power operation mean that scan testing has become a limiting factor in achieving time to market demands without compromising quality of the delivered product or increasing test costs. As a result, using EDA tools for power analysis of device behaviour during scan testing is an important research topic for the semiconductor industry. This thesis describes the design synthesis of the OpenPiton, open research processor, with emphasis on scan insertion, automated test pattern generation (ATPG) and gate level simulation (GLS) steps. Having reviewed scan testing theory and practice, the thesis describes the execution of each of these steps on the OpenPiton design block. Thus, by demonstrating how to apply EDA based synthesis and design for test (DFT) tools to the OpenPiton project, the thesis addresses one of the most difficult problems faced by any new user who wishes to use existing EDA tools for synthesis and scan insertion, namely, the enormous complexity of the tool chains and the huge and confusing volume of related documentation. The OpenPiton project was selected because it allows a user to implement design synthesis by simply adding standard cell library files, a good starting point for research based on scan test. Applying the design flow to a relatively small OpenPiton design block allows many overheads to be eliminated thereby making the flow easier to understand, but it is shown that the techniques can be easily migrated to larger OpenPiton design blocks including synthesis of multicore designs that can mimic today’s large commercial SOC (system on chips) for scan power issues. Additionally, in keeping with the emphasis on mitigating, the thesis shows how a design flow for the OpenPiton design block can be created using several EDA tools, with techniques to support power analysis or estimation being highlighted at various points in the flow. As a result of this work, readers should be able to set up an entire flow and reach a stage of data generation for scan power analysis in a shorter duration. This will allow engineers to focus on new approaches for scan power test mitigation and means that the re-iteration of the flow for data collection will become a much more manageable task.
- Master (Research)