Design of continuous time input pipelined ADCS for advanced CMOS technologies
This thesis presents a new Continuous Time Input Pipeline (CTIP) ADC architecture that has enhanced bandwidth and resolution compared to previously published work. The research carried out contains a comprehensive analysis of the limitations of previous CTIP ADCs architectures and a fundamental overview leads to a new implementation. An all pass filter based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the mid-scale resistive input benefit of CTIP ADCs. Detailed analysis of the properties and requirements to build resetting integrator gain stages are covered in the thesis.
The resetting integrator allows the architecture to be implemented with a Feed-Forward (FF) compensated op-amp using low voltage CMOS processes. Analysis of three stage FF op-amps is presented and a design procedure implementing them is detailed. A novel reset circuit removes the risk of instability in the reset mode. A novel integrate and hold circuit allows the CTIP to operate as an analog frontend with any sampled backend ADC and avoids performance limitations due to the sampling jitter of the backend ADC. Non-linearity and switching distortion issues with the DACs required to build CTIP ADCs are also investigated. A solution to reduce switching distortion when using Tri-level DACs is proposed and a resistive DAC topology to avoid switching distortion is implemented.
This work has been verified by simulation results of a CTIP ADC with 1.2V supply voltage designed in TSMC’s 65nm CMOS technology. The physical design (layout) of the ADC has been implemented and its parasitics were used to carry out extracted simulations. All the circuits used in the final design are suitable for migration to CMOS technologies with sub 1V supply voltages and the CTIP ADC performance will benefit from the speed improvements of advanced CMOS technologies.
- Faculty of Science and Engineering
First supervisorBrendan Mullane
Second supervisorTony Scanlan
Other Funding informationI am very grateful to Analog Devices for funding my project.
Department or School
- Electronic & Computer Engineering