Development and implementation of a platform for the performance characterisation of a 12-bit 25Msps SAR ADC

A measurement platform to characterise the performance of integrated circuits is a critical component in the development of integrated circuit technologies. In the case of this work, the integrated circuit is a 12-bit, 25Msps SAR ADC, fabricated on 65nm CMOS. The ADC integrates an on-chip background digital calibration scheme based on a correlation methodology, correcting for capacitor mismatch. The novel aspect of the ADC is untrimmed ENOB performance of 11-bits at a sample rate of 25Msps for a converter fabricated on a 65nm CMOS process. A measurement platform is developed and implemented, operating at a performance level surpassing that of the ADC, ensuring accurate measurement of the ADC performance parameters, both static and dynamic. The measurement platform consists of test & measurement equipment to power the ADC, apply stimulus to its input and acquire data from its output. A printed circuit board allows the ADC to interface to the measurement equipment. Control of the equipment and processing of the acquired data is implemented in the labview programming environment, allowing measurement automation of the performance parameters. The platform developed successfully characterised the performance of the ADC. The parameters characterised are Integral NonLinearity (INL) error, Differential NonLinearity (DNL) error, Spurious Free Dynamic Range (SFDR), SIgnal to Noise And Distortion (SINAD) and Effective Number Of Bits (ENOB). The platform also proved successful in debugging and verifying the operation of the on-chip calibration by correlation methodology. Proposed further work is the expansion of the platform into a flexible and configurable generalised characterisation platform, to be used in the characterisation of any given ADC. Included in this is the addition of an FPGA module, which would allow the development and real-time implementation of calibration algorithms.