Utilizing multicore architectures to enhance software verification in real-time embedded systems

The hypothesis of this research is that new techniques are required to facilitate software verification on the highly-integrated, but resource constrained, real-time embedded systems; which are widely used in safety-critical applications. Software verification is an essential but expensive undertaking which often consumes as much or more resources than design activities; this is particularly the case in embedded systems that require functional safety. This research explores the existing techniques for software verification on these systems and the verification challenges posed by modern highly-integrated devices. The author then proposes a novel target-level verification approach which addresses some of these challenges. Advances in semiconductor manufacturing processes have fuelled the relentless shrinking of IC design geometries. This has dramatically reduced the area required for each functional block, reduced costs, and allowed more complex circuits to be realised; which has led to the System-on-Chip (SoC) designs which now include multiple processors within a single die. Undoubtedly many benefits result from this increased integration, but one significant drawback is the loss of access to the many signals indicating the internal operational state. Visibility of these signals is essential for many embedded software verification purposes. In parallel with increasing SoC complexity, verification technology has transformed from using full in-circuit emulation, to bond-out devices, to on-chip instrumentation (OCI), each providing less visibility to the execution state of the processor. A key benefit of OCI approaches is the associated reduced physical interface requirements; unfortunately this also limits the real-time data that can be captured and transferred to external analysis tools. The author proposes the alternative of using this OCI in conjunction with a co-processor to perform monitoring and verification tasks on-chip; thus overcoming the interface limitations and enhancing visibility. The experimental platform used to explore the feasibility of using a co-processor and OCI for software verification activities is described; and several case studies are examined. The results demonstrate that this approach does offer a means of addressing several software verification challenges and provides some unique capabilities, but also has some limitations. These benefits and limitations are discussed and suggestions for future work to advance this research topic are provided.